Half Price Standard Code

FOUNDRY PROCESS QUALIFICATION GUIDELINES (Wafer Fabrication Manufacturing Sites)
standard by JEDEC Solid State Technology Association, 05/01/2004

TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS
standard by JEDEC Solid State Technology Association, 07/01/2000

1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V – 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2003

MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS
standard by JEDEC Solid State Technology Association, 11/01/1972

FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS
standard by JEDEC Solid State Technology Association, 10/01/2013

LOW TEMPERATURE STORAGE LIFE
standard by JEDEC Solid State Technology Association, 10/01/2015

HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
standard by JEDEC Solid State Technology Association, 04/01/2014

MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)
standard by JEDEC Solid State Technology Association, 07/01/2007

DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 11/01/2005