Half Price Standard Code

STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SURFACE-MOUNT COMPONENTS
standard by JEDEC Solid State Technology Association, 05/01/2005

ADDENDUM No. 7 to JESD24 – COMMUTATING DIODE SAFE OPERATING AREA TEST PROCEDURE FOR MEASURING dv/dt DURING REVERSE RECOVERY OF POWER TRANSISTORS
Amendment by JEDEC Solid State Technology Association, 08/01/1982

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) – LEAD (Pb) CONTENT
standard by JEDEC Solid State Technology Association, 04/01/2017

CYCLED TEMPERATURE HUMIDITY BIAS LIFE TEST
standard by JEDEC Solid State Technology Association, 07/01/2013

ADDENDUM No. 1 to JESD12 – TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS
Amendment by JEDEC Solid State Technology Association, 08/01/1993

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 09/01/2003

GDDR5 SGRAM
standard by JEDEC Solid State Technology Association, 09/01/2009

NAND Flash Interface Interopability
standard by JEDEC Solid State Technology Association, 06/01/2019

Low Power Double Data Rate 4 (LPDDR4)
standard by JEDEC Solid State Technology Association, 2015

STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 07/01/2001