Half Price Standard Code

SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET)
standard by JEDEC Solid State Technology Association, 06/01/1985

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
standard by JEDEC Solid State Technology Association, 09/01/2004

Customer Notification Process for Disasters
standard by JEDEC Solid State Technology Association, 01/01/2014

STANDARD MANUFACTURERS IDENTIFICATION CODE
standard by JEDEC Solid State Technology Association, 04/01/2009

ADDENDUM No. 6 to JESD24 – THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS
Amendment by JEDEC Solid State Technology Association, 10/01/2001

MARKING PERMANENCY
standard by JEDEC Solid State Technology Association, 03/01/2011

GUIDELINES FOR SUPPLIER PERFORMANCE RATING
standard by JEDEC Solid State Technology Association, 01/01/2009

CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING
standard by JEDEC Solid State Technology Association, 08/01/2017

Low Power Double Data Rate 3 SDRAM (LPDDR3)
standard by JEDEC Solid State Technology Association, 08/01/2015

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS
standard by JEDEC Solid State Technology Association, 08/01/2001